Please see also characterization works (klog#35926) and the model update work (klog#35961).
K1:CAL-CS_PROC_PMC_FREQUENCY_DQ is now available as calibrated frequency noise of PMC in the unit of MHz.
Though this signal is provided by using K1:PSL-PMC_MIXER_MON_OUT_DQ as the error signal and K1:PSL-PMC_PZT_HV_MON_OUT_DQ as the feedback signal,
K1:PSL-PMC_FAST_MON_OUT seems to be better as the feedback signal because HV output channel is probably contaminated by ADC (or circuits at pick up path) noise around UGF.
Or another solution is to use universal whitening filter for HV output channel.
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Calibration factors
Optical gain (from frequency disturbance to K1:PSL-PMC_MIXER_MON_OUT_DQ) was estimated in klog#35960 as 8.5e-7 V/Hz (OLTF fit) and (1.6+/-1.1)e-6 V/Hz (PDH signal). These two optical gains by OLTF fit and by PDH signal were set on FM1 and FM2 of K1:CAL-CS_SUM_PMC_ERR, respectively, and now one by OLTF fit is enabled because using one by OLTF fit induces a systematic bias only on the overall gain. (On the other hand, using optical gain by PDH signal induces frequency dependent systematic bias around UGF.)
PZT efficiency (from K1:PSL-PMC_PZT_HV_MON_OUT_DQ) used in the optical gain estimation above was estimated in klog#35875 as 889kHz/V. This value was set on K1:CAL-CS_SUM_PMC_CTRL_PZT.
Polarity of each factor
According to the relation between the input voltage to PZT and asymmetric resonant shape by radiation pressure (Fig.2 of klog#35875), increasing input voltage seems to increase frequency. So a polarity of PZT efficiency (Hz/V) should be positive. And also, klog#35875 shows same polarity between Slow out and HV out. This fact suggests that U10 as the switchable sign stage is positive because Both Slow board (JGW-D1301827) and U11 of Main board (JGW-D1301823) have "-1" gain and these two stages are only components having negative gain at the downstream of the Slow output path. This assumption about U10 stage is consistent with klog#35949.
Optical gain estimated in klog#35960 includes a factor of -3.16 by U3 of Main board. According to the overplot of measured OLTF and model, Total optical gain seems to be positive. This means the optical gain from frequency to the input of U3 stage is negative. It depends on the phase relation at RF mixer between LO signal and PD signal. But it hasn't probably checked independently yet. Anyway, from the view point of calibration, a polarity of sensing path can be regarded as positive based on the consistency of measured OLTF and model in klog#35960klog#35960.
Finally, we can get calibrated signal as follows.
V_err = (delta_f + H_pzt * V_ctrl) * H_c
<=> delta_f = (1/H_c) * V_err - H_pzt * V_ctrl
where both H_c and H_pzt are positive.
Thoughts about calibrated signal
Spectra of calibrated signal (Red), (1/H_c) * V_err (Green), and H_pzt * V_ctrl (Blue) are shown on the upper left panel in Fig.1. Blue curve corresponds to the past calibration which was provided by using only feedback signal and we can see a difference from better calibration especially above UGF. According to the transfer function between (1/H_c) * V_err (Green) and H_pzt * V_ctrl shown in the right panels in Fig.1 (this TF corresponds to the OLTF model on the front-end calibration), UGF is around 1.3kHz.
One important notice is coherence between these two signals are not so high above 10Hz (see also the lower left panel in Fig.1). I tried to tweak calibration filters but I cannot improve the situation by using digital whitening technique. This fact suggest bad coherence between error and feedback signal comes from ADC or circuit noise at DAQ pick up path instead of numerical rounding issue by digital signal processing. So I also checked coherence between raw error signal (K1:PSL-PMC_MIXER_MON_OUT_DQ), TTFSS output (K1:PSL-PMC_FAST_MON_OUT_DQ), and HV output (K1:PSL-PMC_PZT_HV_MON_OUT_DQ) as shown in the upper panel of Fig.2. Then, HV output has poorer coherence with the error signal than TTFSS output probably due to a low gain by the pomona box at the input port of HV amp (see the lower panel of Fig.2). And also, calibrate spectra of HV output is louder than one of TTFSS output around kHz band. It seems to be a contamination by ADC noise.
From these results, we can conclude that TTFSS output is better as feedback signal for calibration than HV amp output. On the other hand, using HV amp output makes calibration simple. So it's probably good to use universal whitening filter for PMC control signals to mitigate poor SNR at ADC.
I confirmed ADC noise contamination on PMC control signals by using the past measurements of ADC noise as shown in Fig.1.
MIXER_MON, FAST_MON, FAST_OUT1, and HV_OUT are error signal, feedback signal of fast PZT path, error point of slow PZT path and total feedback to PZT, respectively. Fig.1 shows the spectra of these signals during PMC (+IMC) lock as solid lines and ADC noise of each channel as dashed lines.
For HV_OUT (orange curve), noise excess by ADC noise can be seen around 1kHz. On the other hand, FAST_MON (blue curve) doesn't contaminated. And also, calibrated spectra of HV_OUT and FAST_MON is well matched around several hundred Herz band (this fact means, characterization of pomona box is not so bad). So FAST_MON is better than HV_OUT as the feedback signal for calibration. Or 1 stage of z1:p10 whitening for HV_OUT is enough to avoid ADC noise contamination if we can use whitening filter (I'm not sure there is enough space to install a circuit in IOO0 rack), 1 stage of z1:p10 whitening is enough to avoid ADC noise contamination.
Another contamination occurs on FAST_OUT1 below a few Herz. This signal is the error point of slow PZT path using digital servo. According to the past modeling and measurement of PMC control loop (klog#16345 and klog#16367), slow PZT path works from ~3mHz (cross over with thermal path) to 40Hz (cross over with fast PZT path). These fact means current PMC control induces digital control noise below a few Herz though it works fine for a few tens of Herz band. Because ADC readout of FAST_OUT1 is ~+/-100ct during PMC lock (see top panel of Fig.2), this situation may be able to be mitigated by using whitening gain (I'm not sure there is enough space to install a circuit again).
