[Takano, Dan, Hirose, Saito]
Following klog:36916, we continued our attempts to achieve PLL lock. We tested both flat filters and low-pass filters. Although loose locking was achieved, we were unable to add an integrator while maintaining lock. In addition, we were unable to measure the open-loop transfer function successfully.
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First, we confirmed the beat signal between the sub-laser beam and the beam coming from the interferometer. Next, the 100 kHz low-pass filter after the mixer was replaced with a 1.9 MHz low-pass filter. A control filter was then implemented using Moku:Lab, and lock acquisition was attempted by matching the LO frequency to the beat signal frequency. For a flat control filter, the system appeared to be most stable with a gain of -10 dB. Increasing or decreasing the gain from this value resulted in poor locking performance. For a low-pass control filter, higher gains could be used compared to the flat-filter case while maintaining lock. However, as the cutoff frequency was reduced, lock acquisition became increasingly difficult.
The control filters and corresponding beat signals are shown below. In the filter screenshots, the red trace represents the error signal and the blue trace represents the feedback signal.
Flat filter with a gain of -20 dB (Photo 1), corresponding beat signal (Photo 2)
Flat filter with a gain of -10 dB (Photo 3), corresponding beat signal (Photo 4)
Flat filter with a gain of 0 dB (Photo 5), corresponding beat signal (Photo 6)
Low-pass filter with a gain of 0 dB and a cutoff frequency of 100 kHz (Photo 7), corresponding beat signal (Photo 8)
Low-pass filter with a gain of 40 dB and a cutoff frequency of 10 kHz (Photo 9), corresponding beat signal (Photo 10)
Low-pass filter with a gain of 30 dB and a cutoff frequency of 1 kHz (Photo 11), corresponding beat signal (Photo 12)In addition, we attempted to add an integrator while the system was locked using either the flat filter or the low-pass filter. However, the lock was lost after the integrator was enabled. Since the integrator cutoff frequency was set directly to a relatively high value such as 1 kHz, it is possible that the lock could have been maintained if the integrator had been introduced gradually, starting from a much lower frequency. We also attempted to measure the open-loop transfer function while the PLL was locked in order to determine the UGF. However, we were unable to obtain a successful measurement.