Abstract
This work is related to klog#23195, klog#23368 and klog#23566We checked the existence of ADC glitches for all channels on ALS0 rack.
Noise excess in low frequency on the error signal of PLL-Y doesn't seem to be ADC glitches.
Details
Following channels has too loud glitches.They are just monitor ports.
- ADC2_CH04: ALS-Y_PLL_SLOWFB_MON
- ADC2_CH22: ALS-SUM_SLOW_DAQ
ADC noise of each channel is shown in Fig.1-Fig.16
Glitcy channels including very small glitches are as follows.
- ADC0_CH02: ALS-X_PLL_FAST_MON
- ADC0_CH08: ALS-X_PLL_SLOWFB_MON
- ADC0_CH15: unused
- ADC0_CH16: ALS-X_FIB_PDA1
- ADC0_CH17: ALS-X_FIB_PDA2
- ADC0_CH20: ALS-X_BEAT_LO_RFPOWER
- ADC1_CH04: LSC-REFL_PDA2_135_I
- ADC1_CH11: ASC-REFL_QPDA2_DC_SEG4
- ADC1_CH21: LSC-CARM_SERVO_FAST_DAQ
- ADC1_CH26: LSC-REFL_PDA1_56_Q
- ADC2_CH04: ALS-Y_PLL_SLOWFB_MON
- ADC2_CH22: ALS-SUM_SLOW_DAQ
- ADC3_CH01: ASC-REFL_QPDA1_RF17_I1
- ADC3_CH22: ASC-REFL_QPDA1_RF45_Q4
An error signal of PLL-Y has noise excess in low-frequency region.
But ADC noise on that channel (ADC0_CH25 which is shown as blue curve in the top panel of Fig.4) is not loud.
So noise excess comes from the upstream of AA chassis such as CMS chassis.
