[Ikeda, Nakagaki, YamaT]

We moved V2 IO chassis to the IXV room, which had been tested as K1IZ1 in the server room klog#36145.
After solving some troubles, it works fine with 150m fibers between the server room and the 2nd floor of the corner station which are planned to use for K1IX1 as a product version in future observing runs.
Though a stability test for a long term, connection test to RFM network, and connection test to ITMX suspension still remain, the new hardware test with actual infrastructure in the mine was succeeded.
Stability test will be continued until the end of Feb. and remaining connection tests will be done by swapping current ITMX hardware in Mar.

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Accidental shutdown of K1TEST0
During this work, we stopped V2 IO chassis for K1TEST0 instead of one for K1IZ1 in a mistake. For recovering it, rebooting the front-end models and the computer was necessary. Fortunately, K1TEST0 is a Dolphin-free node, so I tried to reboot the front-end computer only with clearing SDF differences of the front-end models on K1TEST0. A details of SDF issue will be reported in klog#36184.

Flipped Tx/Rx fibers
When we launched V2 IO chassis at IXV at first, connection to the 3rd Adnaco board cannot be established. Finally we noticed it's due to a flipped fibers of Rx and Tx. The fiber interfaces of IO chassis and the splice box at the 2nd floor of the corner station are MTP. And also, the interface of the front-end computer (Adnaco PCIe card) is fiber pair ports. On the other had, the interface of the splice box in the server room is a single fiber port instead of a fiber pair port. So a fiber pair connection is easily flipped in the server room and it's difficult to find by the connectivity test with the power meter for the optical fiber. Cabling and tagging rule should be contained in the installation manual for the V2 IO chassis.

Timing error
At the end of this work, we closed IO chassis body and tried to do the cold boot. Then, k1iopiz1 lost the timing synchronization. Strictly speaking, TDS seems to work and duotone signals can be seen on ADC0_CH31. But DT ADC and IRIG-B showed abnormal values and TIM bit in the state word was raised. I tried to restart front-end models and reboot front-end computer, but timing error still remained. During this trial, DT ADC ad IRIG-B showed a drift in the time. I gave up to fix it once and re-tried after coming back to Mozumi, then timing synchronization came back. It might be a large temperature drift of crystal oscillator on the timing slave. Similar phenomena occurred in another IO chassis (IOO, PRs, SRs, etc.). But it's first time to face it around IXV/IYV area. It may be better to take care about the reproducibility for a while.