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osamu.miyakawa - 16:03 Thursday 06 September 2018 (6031) Print this report
IRIG-B 9999xx issue fixed!

Finally IRIG-B 9999xx issue was fixed!

It was a serious and deep problem for these several years.

Problem was something like this;

Timing slave sends a gate signal along 1PPS singal, then clocks start and are sent to ADC and DAC, but ADC starts 1 cycle (16usec) faster somehow, probably by glitch, noise or something.
Realtime loop starts 1 cyckel faster as a result by recieving the signals from the ADC that started 1cycle faster. Then the real time code reads GSP time with 1 cycle faster timing, and then it shows 9999xx on IRIG-B.

There are two solutions;

One is hardwarely to modify to have ADC start slower. However It is not so easy to trace FPGA code on timing slave, it is not so convenient to modify each backplane board or each ADC adapter card.
Another solution is to add a delay of 1cycle on the realtime code, even ADC runs 1 cycle faster already.

Changes in controller.c of RCG2.9.7 are quite simle;

controls@k1ctr2:/opt/rtcds/rtscore/release/src/fe$ diff controller.c.20180906 controller.c
> int irigberror = 0; //Error status for IRIG-B added by Osamu to avoid 9999xx issue
> //Added by Osamu to avoid IRIGB 9999xx issue
>                 irigberror = 1;
>             } else {
>                 irigberror = 0;
> // until here by Osamu
>                 if(irigberror) cycleNum -= 1; //Added by Osamu to avoid IRIGB 9999xx issue

An important point is the location where I changed the cycle number. It is in the special term for the first 3 seconds.
This compensation is performed only within first 3 seconds after the real time code started. In this term, error checking codes are ignored for cycle errors or something.
After 3seconds, the compensation won't work to distingwish actual failures of timing or other troubles while the real time code is running.

I appled this code to k1iy1 that had 999xx on IRIG-B. It seemed to be fixed now. Even if you re-build your IOP model on other RT PCs, it should work as normal if the IOP has no IRIG-B issue, so do not be afraid to build IOP models.

However this is a kind of cheating the cycly anyway. I do not think this would be a serious problem, but if you notice something on k1iy1, please let me know.

Comments to this report:
keiko.kokeyama - 16:37 Thursday 06 September 2018 (6032) Print this report
This is an awesome progress!!
yoshinori.fujii - 22:09 Thursday 06 September 2018 (6040) Print this report

Indeed! thanks a lot Miyakawa-san!

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