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DGS (General)
takahiro.yamamoto - 20:55 Monday 02 May 2022 (20642) Print this report
Timing error on ITMX and ITMY with new ADCs

[Ushiba, YamaT]


- This post is related to the glitch issues on ITMX F3_GAS (klog#20639) and ITMY ACC_H2 (klog#20636)
- Glitch issue was solved by replacing ADC board, ADC adapter board, and ADC internal cable.
- After replacing ADC, timing error occurred on both K1IX1 and K1IY1.
- We can do the local measurements on ITMX and ITMY.
- But measurements with channels on ITMX/ITMY and other RTFEs were affected by this issue.


For DGS experts
In order to investigate glitch issues, we replaced ADC board, ADC adapter board and ADC internal cable.
Glitches vanished and noise level was improved by this replacement.

However, timing error cannot be fixed after ADC replacement.
Now ADC DT on k1iopix1 and k1iopiy1 are "20" [us] (See Fig.1).
This means that timing on ADC delayed as 1-sample on 64kHz (nominal ADC DT is "5" [us])

And also, according to the IRIG-B channel, timing delayed form nominal timing as 4-5us.
(Current value is 7 and nominal is 11 or 12.)
This issue seems to be different from "IRIG-B 999997" problem (e.g. klog#583 and klog#6031).
Maybe 4-5us delay is rounded up to the integer multiples of 1/65536Hz.

In fact, timing duotone signal delayed as 1-sample only on k1iopix1 and k1iopiy1.
Fig.2 shows the duotone ADC signal on some RTFEs.
On k1lsc0 and RTFEs for ETMs, signals across to 0 between the first and the second sample points counted from integer GPS time.
On the other hand, signals across to 0 between the second and the third sample points counted from integer GPS time.

I'm now doubting the difference of the product lot of ADC.
ADCs that we installed today were purchased in FY2021 (S2113340 for IX and S2113341 for IY).

From the view point of noise, we need to replace ADC card form original ones.
We need to solve this problem before starting global control.

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Comments to this report:
takahiro.yamamoto - 9:35 Tuesday 10 May 2022 (20672) Print this report
I checked noisy ADC and revC ADC on the test bench.

Reproducibility of Timing error
New product lots (revC) of ADC were not able to be synchronized also on the test bench.
Situation was same as ITMX (klog#20639) and ITMY (klog#20636)

Possibility of the usage of revC ADC
If we don't use them as the 1st ADC (ADC0), timing error doesn't occur.
But I haven't checked actual timing delay on the signal on the secondary ADC (ADC1), etc. which is revC.
So I need to check it in order to use revC for ADC1.

Reproducibility of loud ADC noise
There is no reproducibility. Glitchy ADC which was used on ITMY seemed to be healthy on the test bench.
On ITMY, ADC noise level of F3 GAS was too loud as shown in Fig.1.
But even if I used same ADC board and measured same channels there is no excess from nominal ADC noise level (see Fig.2).
It seems to be the combination problem of AA chassis and ADC baords.
Images attached to this comment
takahiro.yamamoto - 20:52 Thursday 12 May 2022 (20709) Print this report


- Model cannot be synchronized with revC ADC as ADC0 also on the test bench.
- When revC ADC is used as ADC1 or ADC2, model can be synchronized.
- But signals on revC ADC seem to delay as one sample in 65536Hz.


I tested revC ADC and confirmed that timing error by using revC ADC as ADC0 was reproduced.
"IRIG-B" and "DT ADC" show 5 and 20, respectively.
Nominal value of "IRIB-B" and "DT ADC" are 12 and 5, respectively.
I guess that 7us additional delay occurs by revADC and this delay is rounded up to the integer multiple of 15us (1/65536Hz) on the digital system.

This one sample delay was also reproduced when revC ADC was used as ADC1, ADC2, etc.
By connecting this signal to CH0 of DAC0 in the user model and connecting DAC to ADC on analogue electronics, I injected a duotone signal to CH0 of ADC0, ADC1 and ADC2.

Duotone signal detected on each ADC is shown in Fig.1.
ADC0 and ADC1 are revB. And ADC2 is revC.
Only on revC, detected signal delayed as one sample.

Because amount of delay seems to be stable, revC ADC may be able to use as ADC1, ADC2, etc if 15us delay is acceptable in the control.
But mixture of ADC whose delay is difference makes management and calibration complicated.

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