VIS (IX)takahiro.yamamoto - 13:57 Saturday 04 September 2021 (18152)
Print this reportUpdate plan of filter implementation for ITMX[Ushiba, YamaT]
Because units at BLEND_{LVDT,ACC}{L,T,Y}_IN1 are different between ACC and LVDT, we plan to move integrator at IP_BLEND_ACC{L,T,Y} to IP_ACCBLEND_ACC{L,T,Y} as shown in Fig.1 and Fig.2.
Filters have been already copied like as Fig.3-5. But now IP_ACCBLEND_ACC{L,T,Y}_IN1 are not DQ-ed. In order to recored both before and after integrator, we will turn ON integrator at IP_ACCBLEND_ACC{L,T,Y} (and also turn OFF ones at IP_BLEND_ACC{L,T,Y}) after adding new DQ channels in next DGS maintenance.