DGS (General)takahiro.yamamoto - 16:16 Friday 13 August 2021 (17911)
Print this reportEY0 rack maintenance[Yokozawa, YamaT]
Abstract Channel assignment and cabling of EY0 rack was cleaned up according to JGW-L2113125. Models were also modified accordingly.
Details k1aostmsy (TMS optics) and k1aosey (Baffle PDs) were merged as one model (k1tmsy). Please be careful about channel name was also changed from 'K1:AOS-TMSY_.*' to 'K1:TMS-Y_.*' Filter bank and SDF set point were taken over from old models.
MEDM screens wasn't updated because it's difficult to modify properly because now convention of EX0 and EY0 was completely different. After updating EX0 (maybe next Friday), MEDM screens will be updated.
Because of this modification, channel assign is twisted on k1caley. Now ch#4-7 (OFS gain), and ch#8-11 (Path2 Inj) of the AI#1 are connected to ch#8-11 and ch#4-7 of the AI buffer circuit, respectively. Path2 Inj is planned to connected to ch#1 of the AI#1 in near future (EX0 is already changed as so.) and after then the twisting will be resolved.
Comments to this report:
takahiro.yamamoto - 18:10 Wednesday 18 August 2021 (17944)
Print this report[Ushiba, YamaT]
We fixed bug in k1vistmsy and k1tmsy and new models are now running.
---- When Ushiba-kun unplugged the cable for TMS DCPDs which is connected to ADC1, there is no response on PD channels. At first, we doubted the channel shuffle issue, but ADC1 surely responded on the IOP model. And also I noticed channel values of ADC1 on the IOP model is same as ones of ADC2 on TMS models. On the other hand, PD channels were also connected to ADC1.
Finally, I found that following things by checking generated C-code and fixed this problem by adding a ADC0 block on TMS models. - Even if ADC0 is not used explicitly, the ADC0 block is necessary for each model. - The correspondence between the ADC array (dWord[ii][jj]) and each channel is correct, but the pointer address seems to be wrong.