Reports 1-1 of 1 Clear search Modify search
MIF (General)
takafumi.ushiba - 21:52 Monday 07 June 2021 (17002) Print this report
ALS X arm becomes glichy for 10 minutes

Just report.

I saw error signals of ALS X became glichy from about 21:40 JST.
The gliches almost disappear about 10 minutes later (21:50 JST).

Images attached to this report
Comments to this report:
satoshi.tanioka - 22:17 Tuesday 08 June 2021 (17020) Print this report

Again.

This happens in PLL X not in Y.

Images attached to this comment
tomotada.akutsu - 22:53 Tuesday 08 June 2021 (17021) Print this report

Actually, such glitchy behaviors have been seen for these days (before you increase the fiber amp power output, I guess). Detachar/PEM helps? (e.g. Yuzurihara-kun...)

hirotaka.yuzurihara - 0:03 Wednesday 09 June 2021 (17025) Print this report

Tomorrow I will listen to the situation from Kenta or Tanioka-san and investigate that.

satoshi.tanioka - 7:38 Wednesday 09 June 2021 (17030) Print this report

PLL Y also becomes glithcy now.
But X seems okay.

Images attached to this comment
hirotaka.yuzurihara - 20:35 Wednesday 09 June 2021 (17039) Print this report

Related to this issue, I made the summary page for PLL newly. Even though there is no glithc in PLL, we should have summary page. Comments to this page are welcome.

Next I will start more glitch investigation.

takahiro.yamamoto - 13:23 Thursday 10 June 2021 (17052) Print this report
Spectra of PLL_X and PLL_Y error signals are quite difference (see top left and middle left panels in the attachment)
On the other hand, bottom left panel shows that feedback signals to laser PZT are similar. PLL_X is slightly noise.

Input referred noise are estimated by using the design value of CMS. So they are probably not so accurately.
But for PLL_Y, signal seems to be seen on both error and feedback signal above a few hundred Herz. (see top right and middle right panels.)

CMS parameters should be same (really?) for PLL_X ad PLL_Y. So a monitor channel of the error signal may be contaminated by circuit or digital noise in DAQ path.
(There is no info. about CMS for PLL_Y on JGW Wiki. It is also better to check it.)
Images attached to this comment
hirotaka.yuzurihara - 15:27 Thursday 10 June 2021 (17053) Print this report

Yamamoto-san kindly pointed out the mistake in summary page. There were same figures with incorrect legend.

I fixed that, so the latest summary page should be correct.

 

In addition, I changed the condition of locked PLL. Currently, the locked PLL in summary page means lock of PLL-X and PLL-Y at the same time.

Images attached to this comment
Search Help
×

Warning

×